These years, there has been a considerable interest in practical techniques to improve the yield of LSIs at little sacrifice of performance and area. Recently, we presented a new concept device, called Partially-Programmable Circuit (PPC), which consists of conventional gates, LUTs, and wires, and enhances yield only by implicit logic redundancy (by partial reconfiguration of the LUTs) and redundant wires. In this talk, a novel high-level synthesis (HLS) approach using PPC-realized resources is presented. Considering reconfiguration of the resources after fabrication, our work aims at maximizing yield expectation.