Principal Investigator: Prof. Daniel D. Gajski
Project Title: "Functional Equivalence Verification of Transaction Level Models"
Period of Performance: September 1, 2006 - August 31, 2009
Scope of Work: This project will focus on verification of functional equivalence of Transaction Level (TL) models using formal definition of such models. This research is applicable to a variety of platforms consisting of processors, memories, buses and a variety of IPs and custom hardware components.
Principal Investigator: Prof. Daniel D. Gajski
Project Title: "SER Upgrades for Basic HR5000 Platform"
Period of Performance: June 1, 2006 - May 31, 2008
Scope of Work: The SER environment has been developed by JAXA and UCI under a previous contract. In this work, the SER environment and its databases are updated and extended to include models of a basic HR5000 platform in the SER databases and to add necessary tool support for targeting the HR5000 platform in the SER tool set.
Principal Investigator: Prof. Pai Chou
Project Title: “High-Throughput, Low-Latency, Low-Power, Reliable Wireless Communication in Compact Sensors for Medical Applications”
Period of Performance: September 1, 2006 – August 31, 2007
Scope of Work: This project aims to design and evaluate wireless communication protocols and techniques to achieve high-throughput, low-latency, low-power, reliable wireless communication in ultra-compact wireless sensor systems for real-world, biomedical sensing applications.
Principal Investigator: Prof. Nikil Dutt
Project Title: “Power Estimation of a SoC Design at System-Level”
Period of Performance: April 1, 2006 – March 31, 2007
Scope of Work: This project will establish a power estimation methodology at the system-level design of a SoC and will evaluate its feasibility by applying it to standard bus architectures.
Principal Investigator: Prof. Pai Chou
Project Title: “High-Throughput, Low-Power, Reliable Wireless Communication in Compact Sensors for Medical Applications”
Period of Performance: June 15, 2006 – December 31, 2006
Scope of Work: The objectives of this contract are to refine the problem statement and formal definitions, platform setup, feasibility testing and initial demonstration of the wireless communication protocols for high throughput.
Principal Investigator: Prof. Pai Chou
Project Title: “Low-Latency, Low-Power, Reliable Wireless Communication in Compact Sensors for Medical Applications”
Period of Performance: June 15, 2006 – December 31, 2006
Scope of Work: The objectives of this contract are to refine the problem statement and formal definitions, conduct feasibility testing and to conduct an initial demonstration of the wireless communication protocols for low latency.
Principal Investigator: Prof. Nikil Dutt
Project Title: "Compiler-in-the-Loop ADL-Driven Early Architectural Exploration"
Period of Performance: September 1, 2003 - August 31, 2006
Scope of Work: The goal of this project is to enable efficient exploration of the architectural design space at a high level using an Architectural Description Language (ADL) abstraction to describe the programmable architecture (by providing tools to support early design space exploration ).
Principal Investigator: Prof. Daniel D. Gajski
Project Title: "No-Instruction-Set-Computer (NISC) Technology"
Period of Performance: September 1, 2003 - August 31, 2006
Scope of Work: The objective of this work is to define and prove that NISC concept really works. The additional objective is to find out the gain in simplicity, productivity and performance versus increase in program memory size. Furthermore, we need to define new compiler optimization techniques that will exploit parallelism at register-transfer levels for the NISC. (Note that NISC is not a VLIW although other multi- or hyper-threading could be applied)
Principal Investigator: Prof. Daniel D. Gajski
Project Title: "System-On-Chip Environment (SCE) Testing"
Period of Performance: October 1, 2003 - May 31, 2006
Scope of Work: Center for Embedded Computer Systems (CECS) will develop a System-on-Chip Environment ("SCE") that will translate system specification in SpecC language into cycle accurate design representation for simulation estimation, verification and synthesis.
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